1. Field of the Invention
The present invention relates to a semiconductor device and method of manufacturing the semiconductor device, and more particularly, to a semiconductor device with a structure where source regions, drain regions and the like are elevated on a surface of a semiconductor silicon substrate and a method of manufacturing such a semiconductor device.
2. Description of the related art
With recent year's reduction in size and weight of electric/electronic components, the structure has been made finer in semiconductor devices such as DRAM and the like provided with memory cells. In such semiconductor devices with the finer structure, the effect of electric field is not small on the source region, drain region and the like. For the purpose of reducing the effect of electric field and the like, the semiconductor device such as DRAM and the like with memory cells has adopted an elevated source structure provided on the surface of the semiconductor silicon substrate, an elevated drain structure provided on the surface of the semiconductor silicon substrate, and the like.
The elevated source structure, the elevated drain structure and the like are generally provided on a semiconductor silicon substrate with an impurity diffusion structure called LDD (Lightly Doped Drain), oxide film as an element isolation region called STI (Shallow Trench Isolation) and the like.
As an example, FIG. 1 shows a partial structure of DRAM prior to formation of the elevated source structure, elevated drain structure and the like.
As shown in FIG. 1, the structure prior to formation of the elevated source structure, elevated drain structure and the like is obtained by removing an unnecessary silicon nitride film by etching operation from a multilayer structure including the semiconductor silicon substrate 1, gate wiring 2 separately provided on the semiconductor silicone substrate 1, the silicon nitride film covering the semiconductor silicon substrate including the gate wiring 2 and the like.
In addition, the semiconductor silicon substrate 1 has an impurity diffusion structure 3 required to operate the DRAM, oxide film 4 and the like provided by well-know means.
As shown in FIG. 2, it is considered that each elevated structure 501 representing the elevated source structure, elevated drain structure and the like is formed by performing selective epitaxial growth operation on a region formed by the surface of the semiconductor silicon substrate and the side wall of the silicon nitride film of the gate wiring.
However, when the selective epitaxial growth operation is actually performed, such a case sometimes occurs that the elevated structure 501 is not obtained that indicates the ideal elevated source structure, elevated drain structure and the like as shown in FIG. 2, and an inclined plane occurs called a facet that has the plane direction of (111) or (311) in an end portion of STI provided on the semiconductor silicon substrate. Explaining with an example in FIG. 3, an inclined portion 6 in FIG. 3 corresponds to the facet.
An occurrence of such a facet results in a following problem.
In other words, in performing operation such as implantation of various ions and the like on the semiconductor silicon substrate 1 from above the substrate as viewed in FIG. 3, the distribution of the ions in depth direction such that the ions reach varies between a portion with no facet generated and another portion with the facet generated, and therefore, it is difficult to control implantation of various ions in the semiconductor silicon substrate.
FIG. 4 schematically shows a state where contacts 7 are respectively provided on the elevated structures 501 and 502 representing the elevated source structure, elevated drain structure and the like. In addition, in FIG. 4, an oxide film not shown is provided around the contacts 7.
As shown in FIG. 4, when the elevated structures 501 and 502 are formed and then the contacts 7 of tungsten or the like are provided on the elevated structures, the area of contact between the elevated structure and contact 7 varies for each of the contacts, and a case arises the resistance of the contact differs from one another.
Further, in addition to variations in the contact area, the distance from the bottom of the contact 7 to the semiconductor silicon substrate 1 fluctuates for each of the contacts 7, and due to the fluctuations, another fluctuations may occur in the effect of impurities leaking from the contact on the semiconductor silicon substrate.
There has been a problem that performance of the finally obtained semiconductor device is not stable due to the factors resulting from the facet.
Since the problem arises due to the occurrence of the facet, it is proposed forming the side wall of the gate wiring with two types of oxide films while devising the shape to suppress the occurrence of the facet (see JP 2000-49348).